In the conventional art various forms of error detection and correction are utilized to correct errors in memories, such as caches, system memory, frame buffers and the like that are implemented using static and dynamic random access memory (RAM), read only memory (ROM), and the like. A conventional memory device 100 is illustrated in FIG. 1. The memory device includes an array of memory cells 110, 120, a row decoder 130, a column decoder 140, and error detection/correction logic 150. Typically, the array of memory cells for storing data 110 is extended with additional memory cells for storing error detecting and/or correcting codes 120. The memory cells for storing the error detection/correction codes 120 store a quantity derived from the memory cells utilized for storing data 110. The error detection/correction codes allow corrupted data to be detected and corrected most of the time. One conventional error detecting technique extends every 8 bits of data with an additional parity bit used for detecting a single bit error. One conventional error technique extends every 64 bits of data with an additional 8 bits of error correcting code (ECC) to detect and correct single bit errors and to detect double-bit errors without correction.
Other techniques for detecting and correcting multi-bit errors have been developed. However, conventional methods for detecting and correction multi-bit errors consume a large portion of the memory cell array and/or result in undesirable memory latency.